1. Field of the Invention
The present invention relates to a method for correcting a layout pattern and a method for manufacturing a photomask, and more particularly, to a method for correcting a layout pattern including a contact via pattern overlapping a conducting line pattern and a method for manufacturing a photomask thereof.
2. Description of the Prior Art
In semiconductor manufacturing processes, in order to transfer an integrated circuit onto a semiconductor wafer, the integrated circuits from a database are first designed as a layout pattern and a photomask is then manufactured according to the layout pattern. Patterns on the photomask may then be able to be transferred to the semiconductor wafer. The steps mentioned above may be regarded as a photolithographic process. The layout pattern has to be extremely accurate for forming delicate integrated circuits so as to align with the patterns of the previous and following steps.
In the photolithographic process, deviations often occur when the patterns on the photomask are transferred onto the wafer surface and jeopardize the performance of the semiconductor device. Such deviations are usually related to the alignment accuracy condition of the exposure machines. If a contact via pattern is shifted by mis-alignment, electrical properties of a semiconductor device may be influenced especially for the semiconductors of multilevel interconnects where the contact via pattern is designed for overlapping the upper and the lower conducting line pattern.
In the conventional method for correcting layout patterns, the conducting line pattern is corrected to compensate the influence of mis-alignment, especially for the conducting line patterns with predetermined parts overlapping contact via patterns. The effective overlapping area between the contact via pattern and the modified conducting line pattern will not be affected, even if mis-alignments really occur.
Additionally, as the complexity and integration of integrated circuits continue to progress, the design rules of lines width and space between lines or devices become finer for photolithographic processes. However, the width is influenced by the exposure wavelength used in the lithographic process, and extremely small space may not be obtained through a single exposure process. Therefore, a double-exposure technique has been developed for decomposing a target pattern into two separated patterns, which are then transferred to a photoresist layer by two exposure processes successively. However, the conventional method for correcting layout patterns may not be suitable for the double-exposure technique, since the space between conducting line patterns is close to a critical space value, and the alignment condition between two exposure processes has to be also considered. In addition, a self-aligned via (SAV) design is preferably employed with the double-exposure technique, and the size of the contact via may not be further modified by tuning related etching processes under the self-aligned via design. Therefore, the modification of the contact via pattern becomes more important.